Power semiconductor mold and trim/form engineer
Direct employment
Refresh at 2 years ago
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2 Apply
Suzhou
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Job responsibilities
b. Job description1) Responsible from design review of new products, participate Packageand substrate(Lead frame and DBC) design review, optimize design, process characterization, generate related spec and work instruction, to be owner of qualification and customers samples to complete product qualification, initial training of operation2) Lead potential failure modes review to define RPN into DFEMA and find counter measure to optimize design for yield, cost, quality, reliability, manufacturability, cycle time3) Lead supplier to design required tools and jig such like mold die, trim/form dies, magazine, tubes, or tray4) Characterize and generate report for mold , trim and from related failure modes and key parameters of output variables according to D/PFMEA5) Optimize process recipe, parameters, tools, jigs to meet die attach cost, quality, yield, UPH, reliability, manufacturability to hands over to operation department6) Validate design rule by process characterization 7) Generate process quality specs, recipe, D/PFMEA, Control plan, work instruction to train operation8) Resolve technical issues from characterization, qualification, and customer samples9) Owner of correspond process to meet required process success criteria10) Generate new equipment PO spec leading cross functional team from operation and support department
Job Requirements
a. Requirements1) University graduated major in Physics, Chemistry, mechanical engineering, Electronics engineering, material science, or equivalent2) Min 3 years' experience in Discrete or Module semiconductor mold, trim and form process 3) Epoxy mold compound properties and its reliability failures knowledge 4) Trim/From mechanical design understanding against delamination, package crack and bent lead5) JMP, Minitab DOE or other statistical analysis skill will get advantages6) Be familiar with design, process FMEA, Control plan generation7) In-depth knowledge of power electronic packages and processes8) Fundamental understanding of package design and material properties9) Knowledge of power packages processes 10) Understanding of semiconductor material properties and their influence on semiconductor device behavior11) Able to understand thermo/mechanical simulation and JMP data analysis tools is strongly desired12) Excellent interpersonal, verbal, and written English communication skills13) Ability to demonstrate great attention to detail14) Are a proven self-starter
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